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application note ds034 (v1.2) august 10, 2000 www.xilinx.com 1 1-800-255-7778 introduction ? industry's first totalcmos? pld - both cmos design and process technologies fast zero power (fzp?) design technique provides ultra-low power and very high speed ieee 1149.1-compliant, jtag testing capability - four pin jtag interface (tck, tms, tdi, tdo) - ieee 1149.1 tap controller - jtag commands include: bypass, sample/preload, extest, usercode, idcode, highz 3.3v, in-system programmable (isp) using the jtag interface - on-chip supervoltage generation - isp commands include: enable, erase, program, verify - supported by multiple isp programming plat- forms high speed pin-to-pin delays of 10 ns ultra-low static power of less than 100 a 100% routable with 100% utilization while all pins and all macrocells are fixed deterministic timing model that is extremely simple to use four clocks available programmable clock polarity at every macrocell support for asynchronous clocking innovative xpla? architecture combines high-speed with extreme flexibility 1000 erase/program cycles guaranteed 20 years data retention guaranteed logic expandable to 37 product terms pci compliant advanced 0.5 e 2 cmos process security bit prevents unauthorized access design entry and verification using industry standard and xilinx cae tools reprogrammable using industry standard device programmers innovative control term structure provides either sum terms or product terms in each logic block for: - programmable 3-state buffer - asynchronous macrocell register preset/reset - programmable global 3-state pin facilitates "bed of nails" testing without using logic resources - available in plcc, vqfp, and pqfp packages - available in both commercial and industrial grades description the xcr3128 cpld (complex programmable logic device) is the third in a family of coolrunner ? cplds from xilinx. these devices combine high speed and zero power in a 128 macrocell cpld. with the fzp design technique, the xcr3128 offers true pin-to-pin speeds of 10 ns, while simultaneously delivering power that is less than 100 a at standby without the need for ? turbo-bits ? or other power-down schemes. by replacing conventional sense amplifier methods for implementing product terms (a tech- nique that has been used in plds since the bipolar era) with a cascaded chain of pure cmos gates, the dynamic power is also substantially lower than any competing cpld. these devices are the first totalcmos plds, as they use both a cmos process technology and the pat- ented full cmos fzp design technique. for 5v applica- tions, xilinx also offers the high speed xcr5128 cpld that offers these features in a full 5v implementation. the xilinx fzp cplds utilize the patented xpla (extended programmable logic array) architecture. the xpla architecture combines the best features of both pla and pal type structures to deliver high speed and flexible logic allocation that results in superior ability to make design changes with fixed pinouts. the xpla structure in each logic block provides a fast 10 ns pal path with five dedicated product terms per output. this pal path is joined by an additional pla structure that deploys a pool of 32 product terms to a fully programmable or array that can allocate the pla product terms to any output in the logic block. this combination allows logic to be allocated effi- ciently throughout the logic block and supports as many as 37 product terms on an output. the speed with which logic is allocated from the pla array to an output is only 2.5 ns, regardless of the number of pla product terms used, which results in worst case t pd ? s of only 12.5 ns from any pin to any other pin. in addition, logic that is common to multiple outputs can be placed on a single pla product term and shared across multiple outputs via the or array, effectively increasing design density. the xcr3128 cplds are supported by industry standard cae tools (cadence/orcad, exemplar logic, mentor, synopsys, synario, viewlogic, and synplicity), using text (abel, vhdl, verilog) and/or schematic entry. design ver- ification uses industry standard simulators for functional and timing simulation. development is supported on per- sonal computer, sparc, and hp platforms. device fitting uses a xilinx developed tool, xpla professional (available on the xilinx web site). 0 xcr3128: 128 macrocell cpld ds034 (v1.2) august 10, 2000 0 14* product specification r
r xcr3128: 128 macrocell cpld ds034 (v1.2) august 10, 2000 www.xilinx.com 2 1-800-255-7778 the xcr3128 cpld is electrically reprogrammable using industry standard device programmers from vendors such as data i/o, bp microsystems, sms, and others. the xcr3128 also includes an industry-standard, ieee 1149.1, jtag interface through which in-system program- ming (isp) and reprogramming of the device is supported. xpla architecture figure 1 shows a high level block diagram of a 128 macro- cell device implementing the xpla architecture. the xpla architecture consists of logic blocks that are interconnected by a zero-power interconnect array (zia). the zia is a vir- tual crosspoint switch. each logic block is essentially a 36v16 device with 36 inputs from the zia and 16 macro- cells. each logic block also provides 32 zia feedback paths from the macrocells and i/o pins. from this point of view, this architecture looks like many other cpld architectures. what makes the coolrunner family unique is what is inside each logic block and the design technique used to implement these logic blocks. the contents of the logic block will be described next. figure 1: xilinx xpla architecture logic block i/o 36 16 16 36 16 16 mc0 mc1 mc15 i/o mc0 mc1 mc15 logic block i/o 36 16 16 36 16 16 mc0 mc1 mc15 i/o mc0 mc1 mc15 zia logic block logic block logic block i/o 36 16 16 36 16 16 mc0 mc1 mc15 i/o mc0 mc1 mc15 logic block logic block i/o 36 16 16 36 16 16 mc0 mc1 mc15 i/o mc0 mc1 mc15 sp00464 logic block
r xcr3128: 128 macrocell cpld 3 www.xilinx.com ds034 (v1.2) august 10, 2000 1-800-255-7778 logic block architecture figure 2 illustrates the logic block architecture. each logic block contains control terms, a pal array, a pla array, and 16 macrocells. the six control terms can individually be con- figured as either sum or product terms, and are used to control the preset/reset and output enables of the 16 mac- rocells ? flip-flops. the pal array consists of a programma- ble and array with a fixed or array, while the pla array consists of a programmable and array with a programma- ble or array. the pal array provides a high speed path through the array, while the pla array provides increased product term density. each macrocell has five dedicated product terms from the pal array. the pin-to-pin t pd of the xcr3128 device through the pal array is 10 ns. if a macrocell needs more than five product terms, it simply gets the additional product terms from the pla array. the pla array consists of 32 product terms, which are available for use by all 16 macro- cells. the additional propagation delay incurred by a mac- rocell using one or all 32 pla product terms is just 2.5 ns. so the total pin-to-pin t pd for the xcr3128 using six to 37 product terms is 12.5 ns (10 ns for the pal + 2.5 ns for the pla). figure 2: xilinx xpla logic block architecture to 16 macrocells 6 5 control pal array 36 zia inputs pla array (32) sp00435a
r xcr3128: 128 macrocell cpld ds034 (v1.2) august 10, 2000 www.xilinx.com 4 1-800-255-7778 macrocell architecture figure 3 shows the architecture of the macrocell used in the coolrunner family. the macrocell consists of a flip-flop that can be configured as either a d- or t-type. a d-type flip-flop is generally more useful for implementing state machines and data buffering. a t-type flip-flop is generally more useful in implementing counters. all coolrunner fam- ily members provide both synchronous and asynchronous clocking and provide the ability to clock off either the falling or rising edges of these clocks. these devices are designed such that the skew between the rising and falling edges of a clock are minimized for clocking integrity. there are four clocks available on the xcr3128 device. clock 0 (clk0) is designated as the "synchronous" clock and must be driven by an external source. clock 1 (clk1), clock 2 (clk2), and clock 3 (clk3) can either be used as a syn- chronous clock (driven by an external source) or as an asynchronous clock (driven by a macrocell equation). the timing for asynchronous clocks is different in that the t co time is extended by the amount of time that it takes for the signal to propagate through the array and reach the clock network, and the t su time is reduced. two of the control terms (ct0 and ct1) are used to control the preset/reset of the macrocell ? s flip-flop. the pre- set/reset feature for each macrocell can also be disabled. note that the power-on reset leaves all macrocells in the "zero" state when power is properly applied. the other four control terms (ct2-ct5) can be used to control the output enable of the macrocell ? s output buffers. the reason there are as many control terms dedicated for the output enable of the macrocell is to insure that all coolrunner devices are pci compliant. the macrocell ? s output buffers can also be always enabled or disabled. all coolrunner devices also provide a global 3-state (gts) pin, which, when enabled and pulled low, will 3-state all the outputs of the device. this pin is provided to support "in-circuit testing" or "bed-of-nails" testing. there are two feedback paths to the zia: one from the mac- rocell, and one from the i/o pin. the zia feedback path before the output buffer is the macrocell feedback path, while the zia feedback path after the output buffer is the i/o pin zia path. when the macrocell is used as an output, the output buffer is enabled, and the macrocell feedback path can be used to feedback the logic implemented in the mac- rocell. when the i/o pin is used as an input, the output buffer will be 3-stated and the input signal will be fed into the zia via the i/o feedback path, and the logic imple- mented in the buried macrocell can be fed back to the zia via the macrocell feedback path. it should be noted that unused inputs or i/os should be properly terminated (see the section on ? terminations ? on page 9 in this data sheet and the application note terminating unused i/o pins in xilinx xpla1 and xpla2 coolrunner ? cplds ). figure 3: xcr3128 macrocell architecture ct2 ct3 ct4 ct5 v cc gnd init (p or r) d/t q clk0 clk0 pa l la clk1 clk1 to zia gnd ct0 ct1 gnd gts clk2 clk2 clk3 clk3 sp00457
r xcr3128: 128 macrocell cpld 5 www.xilinx.com ds034 (v1.2) august 10, 2000 1-800-255-7778 simple timing model figure 4 shows the coolrunner timing model. the cool- runner timing model looks very much like a 22v10 timing model in that there are three main timing parameters, including t pd , t su , and t co . in other competing architec- tures, the user may be able to fit the design into the cpld, but is not sure whether system timing requirements can be met until after the design has been fit into the device. this is because the timing models of competing architectures are very complex and include such things as timing dependen- cies on the number of parallel expanders borrowed, shar- able expanders, varying number of x and y routing channels used, etc. in the xpla architecture, the user knows up front whether the design will meet system timing requirements. this is due to the simplicity of the timing model. totalcmos design technique for fast zero power xilinx is the first to offer a totalcmos cpld, both in pro- cess technology and design technique. xilinx employs a cascade of cmos gates to implement its sum of products instead of the traditional sense amp approach. this cmos gate implementation allows xilinx to offer cplds which are both high performance and low power, breaking the para- digm that to have low power, you must have low perfor- mance. refer to figure 5 and table 1 showing the i cc vs. frequency of our xcr3128 totalcmos cpld (data taken w/eight up/down, loadable 16 bit counters at 3.3v, 25 c). figure 4: coolrunner timing model output pin input pin sp00441 t pd_pal = combinatorial pal only t pd_pla = combinatorial pal + pla output pin input pin dq registered t su_pal = pal only t su_pla = pal + pla registered t co global clock pin
r xcr3128: 128 macrocell cpld ds034 (v1.2) august 10, 2000 www.xilinx.com 6 1-800-255-7778 jtag testing capability jtag is the commonly-used acronym for the boundary scan test (bst) feature defined for integrated circuits by ieee standard 1149.1. this standard defines input/output pins, logic control functions, and commands which facilitate both board and device level testing without the use of spe- cialized test equipment. bst provides the ability to test the external connections of a device, test the internal logic of the device, and capture data from the device during normal operation. bst provides a number of benefits in each of the following areas: testability - allows testing of an unlimited number of interconnects on the printed circuit board - testability is designed in at the component level - enables desired signal levels to be set at specific pins (preload) - data from pin or core logic signals can be examined during normal operation reliability - eliminates physical contacts common to existing test fixtures (e.g., "bed-of-nails") - degradation of test equipment is no longer a concern - facilitates the handling of smaller, surface-mount components - allows for testing when components exist on both sides of the printed circuit board cost - reduces/eliminates the need for expensive test equipment - reduces test preparation time - reduces spare board inventories the xilinx xcr3128's jtag interface includes a tap port and a tap controller, both of which are defined by the ieee 1149.1 jtag specification. as implemented in the xilinx figure 5: i cc vs. frequency @ v cc = 3.3v, 25c table 1: i cc vs. frequency (v cc = 3.3v, 25 c) frequency (mhz) 0 1 20 40 60 80 100 typical i cc (ma) .03 .06 12 24 35 46 63 frequency (mhz) sp00471 0 20406080 0 20 40 60 80 100 120 140 i cc (ma) 100
r xcr3128: 128 macrocell cpld 7 www.xilinx.com ds034 (v1.2) august 10, 2000 1-800-255-7778 xcr3128, the tap port includes four of the five pins (refer to table 2 ) described in the jtag specification: tck, tms, tdi, and tdo. the fifth signal defined by the jtag specifi- cation is trst* (test reset). trst* is considered an optional signal, since it is not actually required to perform bst or isp. the xilinx xcr3128 saves an i/o pin for gen- eral purpose use by not implementing the optional trst* signal in the jtag interface. instead, the xilinx xcr3128 supports the test reset functionality through the use of its power up reset circuit, which is included in all xilinx cplds. the pins associated with the power up reset circuit should connect to an external pull-up resistor to keep the jtag signals from floating when they are not being used. in the xilinx xcr3128, the four mandatory jtag pins each require a unique, dedicated pin on the device. however, if jtag and isp are not desired in the end-application, these pins may instead be used as additional general i/o pins. the decision as to whether these pins are used for jtag/isp or as general i/o is made when the jedec file is generated. if the use of jtag/isp is selected, the dedi- cated pins are not available for general purpose use. how- ever, unlike competing cpld ? s, the xilinx xcr3128 does allow the macrocell logic associated with these dedicated pins to be used as buried logic even when jtag/isp is selected. table 3 defines the dedicated pins used by the four mandatory jtag signals for each of the xcr3128 package types. the jtag specifications defines two sets of commands to support boundary-scan testing: high-level commands and low-level commands. high-level commands are executed via board test software on an a user test station such as automated test equipment, a pc, or an engineering work- station (ews). each high-level command comprises a sequence of low level commands. these low-level com- mands are executed within the component under test, and therefore must be implemented as part of the tap control- ler design. the set of low-level boundary-scan commands implemented in the xilinx xcr3128 is defined in ta b l e 4 . by supporting this set of low-level commands, the xcr3128 allows execution of all high-level boundary-scan commands. table 2: jtag pin description pin name description tck test clock output clock pin to shift the serial data and instructions in and out of the tdi and tdo pins, respectively. tck is also used to clock the tap controller state machine. tms test mode select serial input pin selects the jtag instruction mode. tms should be driven high during user mode operation. tdi test data input serial input pin for instructions and test data. data is shifted in on the rising edge of tck. tdo test data output serial output pin for instructions and test data. data is shifted out on the falling edge of tck. the signal is tri-stated if data is not being shifted out of the device. table 3: xcr3128 jtag pinout by package type device xcr3128 (pin number / macrocell #) tck tms tdi tdo 84-pin plcc 62 / 96 (f15) 23 / 48 (c15) 14 / 32 (b15) 71 / 112 (g15) 100-pin pqfp 64 / 96 (f15) 17 / 48 (c15) 6 / 32 (b15) 75 / 112 (g15) 100-pin vqfp 62 / 96 (f15) 15 / 48 (c15) 4 / 32 (b15) 73 / 112 (g15) 128-pin tqfp 82 / 96 (f15) 21 / 48 (c15) 8 / 32 (b15) 95 / 112 (g15) 160-pin pqfp 99 / 96 (f15) 22 / 48 (c15) 9 / 32 (b15) 112/ 112 (g15)
r xcr3128: 128 macrocell cpld ds034 (v1.2) august 10, 2000 www.xilinx.com 8 1-800-255-7778 3.3v in-system programming (isp) isp is the ability to reconfigure the logic and functionality of a device, printed circuit board, or complete electronic sys- tem before, during, and after its manufacture and shipment to the end customer. isp provides substantial benefits in each of the following areas: design - faster time-to-market - debug partitioning and simplified prototyping - printed circuit board reconfiguration during debug - better device and board level testing manufacturing - multi-functional hardware - reconfigurability for test - eliminates handling of "fine lead-pitch" components for programming - reduced inventory and manufacturing costs - improved quality and reliability field support - easy remote upgrades and repair - support for field configuration, re-configuration, and customization the xilinx xcr3128 allows for 3.3v, in-system program- ming/reprogramming of its eeprom cells via its jtag interface. an on-chip charge pump eliminates the need for externally-provided supervoltages, so that the xcr3128 may be easily programmed on the circuit board using only the 3.3-volt supply required by the device for normal opera- tion. a set of low-level isp basic commands implemented in the xcr3128 enable this feature. the isp commands implemented in the xilinx xcr3128 are specified in ta b l e 5 please note that an enable command must precede all isp commands unless an enable command has already been given for a preceding isp command and the device has not gone through a test-logic/rest tap controller state. see also table 5 programming specifications. table 4: xcr3128 low-level jtag boundary-scan commands instruction (instruction code) register used description sample/preload (0010) boundary-scan register the mandatory sample/preload instruction allows a snapshot of the normal operation of the component to be taken and examined. it also allows data values to be loaded onto the latched parallel outputs of the boundary-scan shift-register prior to selection of the other boundary-scan test instructions. extest (0000) boundary-scan register the mandatory extest instruction allows testing of off-chip circuitry and board level interconnections. data would typically be loaded onto the latched parallel outputs of boundary-scan shift-register using the sample/preload instruction prior to selection of the extest instruction. bypass (1111) bypass register places the 1 bit bypass register between the tdi and tdo pins, which allows the bst data to pass synchronously through the selected device to adjacent devices during normal device operation. the bypass instruction can be entered by holding tdi at a constant high value and completing an instruction-scan cycle. idcode (0001) boundary-scan register selects the idcode register and places it between tdi and tdo, allowing the idcode to be serially shifted out of tdo. the idcode instruction permits blind interrogation of the components assembled onto a printed circuit board. thus, in circumstances where the component population may vary, it is possible to deter- mine what components exist in a product. highz (0101) bypass register the highz instruction places the component in a state in which all of its system logic outputs are placed in an inactive drive state (e.g., high impedance). in this state, an in-circuit test system may drive signals onto the connections normally driven by a component output without incurring the risk of damage to the compo- nent. the highz instruction also forces the bypass register between tdi and tdo.
r xcr3128: 128 macrocell cpld 9 www.xilinx.com ds034 (v1.2) august 10, 2000 1-800-255-7778 terminations the coolrunner xcr3128 cplds are totalcmos devices. as with other cmos devices, it is important to consider how to properly terminate unused inputs and i/o pins when fabricating a pc board. allowing unused inputs and i/o pins to float can cause the voltage to be in the linear region of the cmos input structures, which can increase the power consumption of the device. the xcr3128 cplds have programmable on-chip pull-down resistors on each i/o pin. these pull-downs are automatically activated by the fitter software for all unused i/o pins. note that an i/o macrocell used as buried logic that does not have the i/o pin used for input is considered to be unused, and the pull-down resistors will be turned on. we recommend that any unused i/o pins on the xcr3128 device be left uncon- nected. there are no on-chip pull-down structures associated with the dedicated input pins. xilinx recommends that any unused dedicated inputs be terminated with external 10k ? pull-up resistors. these pins can be directly connected to v cc or gnd, but using the external pull-up resistors main- tains maximum design flexibility should one of the unused dedicated inputs be needed due to future design changes. when using the jtag/isp functions, it is also recom- mended that 10k ? pull-up resistors be used on each of the pins associated with the four mandatory jtag signals. let- ting these signals float can cause the voltage on tms to come close to ground, which could cause the device to enter jtag/isp mode at unspecified times. see the appli- cation notes jtag and isp overview for xilinx xpla1 and xpla2 cplds and terminating unused i/o pins in xilinx xpla1 and xpla2 coolrunner cplds for more informa- tion. jtag and isp interfacing a number of industry-established methods exist for jtag/isp interfacing with cpld ? s and other integrated cir- cuits. the xilinx xcr3128 supports the following methods: pc parallel port workstation or pc serial port embedded processor automated test equipment third party programmers high-end jtag and isp tools a boundary-scan description language (bsdl) descrip- tion of the xcr3128 is also available from xilinx for use in test program development. for more details on jtag and isp for the xcr3128, refer to the related application note: jtag and isp overview for xilinx xpla1 and xpla2 cplds . table 5: programming specifications symbol parameter min. max. unit dc parameters v ccp v cc supply program/verify 3.0 3.6 v i ccp i cc limit program/verify 200 ma v ih input voltage (high) 2.0 v v il input voltage (low) 0.8 v v sol output voltage (low) 0.5 v v soh output voltage (high) 2.4 v tdo_i ol output current (low) 8 ma tdo_i oh output current (high) -8 ma ac parameters f max clk maximum frequency 10 mhz pwe pulse width erase 100 ms pwp pulse width program 10 ms pwv pulse width verify 10 s init initialization time 100 s tms_su tms setup time before tck = 10 ns tdi_su tdi setup time before tck = 10 ns tms_h tms hold time after tck = 25 ns tdi_h tdi hold time after tck = 25 ns tdo_co tdo valid after tck 40 ns
r xcr3128: 128 macrocell cpld ds034 (v1.2) august 10, 2000 www.xilinx.com 10 1-800-255-7778 absolute maximum ratings 1 operating range dc electrical characteristics for commercial grade devices commercial: 0 c t amb +70 c; 3.0v v cc 3.6v symbol parameter min. max. unit v cc supply voltage 2 -0.5 7.0 v v i input voltage -1.2 v cc + 0.5 v v out output voltage -0.5 v cc + 0.5 v i in input current -30 30 ma i out output current -100 100 ma t j maximum junction temperature -40 150 c t str storage temperature -65 150 c notes: 1. stresses above those listed may cause malfunction or permanent damage to the device. this is a stress rating only. functional operation at these or any other condition above those indicated in the operational and programming specification is not implied. 2. the chip supply voltage must rise monotonically. product grade temperature voltage commercial 0 to +70 c3.3v 10% industrial -40 to +85 c 3.3v 10% symbol parameter test conditions min. max. unit v il input voltage low v cc = 3.0v 0.8 v v ih input voltage high v cc = 3.6v 2.0 v v i input clamp voltage v cc = 3.0v, i in = -18 ma -1.2 v v ol output voltage low v cc = 3.0v, i ol = 8 ma 0.5 v v oh output voltage high v cc = 3.0v, i oh = -8 ma 2.4 v i i input leakage current v in = 0 to v cc -10 10 a i oz 3-stated output leakage current v in = 0 to v cc -10 10 a i ccq 1 standby current v cc = 3.6v, t amb = 0 c60 a i ccd 1, 2 dynamic current v cc = 3.6v, t amb = 0 c at 1 mhz 2 ma v cc = 3.6v, t amb = 0 c at 50 mhz 50 ma i os short circuit output current 3 one pin at a time for no longer than 1 second -50 -100 ma c in input pin capacitance 3 t amb = 25 c, f = 1 mhz 8 pf c clk clock input capacitance 3 t amb = 25 c, f = 1mhz 5 12 pf c i/o i/o pin capacitance 3 t amb = 25 c, f = 1mhz 10 pf notes: 1. see table 1 on page 6 for typical values. 2. this parameter measured with a 16-bit, loadable up/down counter loaded into every logic block, with all outputs disabled and unloaded. inputs are tied to v cc or ground. this parameter guaranteed by design and characterization, not testing. 3. typical values, not tested.
r xcr3128: 128 macrocell cpld 11 www.xilinx.com ds034 (v1.2) august 10, 2000 1-800-255-7778 ac electrical characteristics 1 for commercial grade devices commercial: 0 c t amb +70 c; 3.0v v cc 3.6v symbol parameter 10 12 15 unit min. max. min. max. min. max. t pd_pal propagation delay time, input (or feedback node) to output through pal 210212215ns t pd_pla propagation delay time, input (or feedback node) to output through pal + pla 3 12.5 3 14.5 3 17.5 ns t co clock to out (global synchronous clock from pin) 272829ns t su_pal setup time (from input or feedback node) through pal 6 7 8 ns t su_pla setup time (from input or feedback node) through pal + pla 8.5 9.5 10.5 ns t h hold time 0 0 0 ns t ch clock high time 3 4 4 ns t cl clock low time 3 4 4 ns t r input rise time 20 20 20 ns t f input fall time 20 20 20 ns f max1 maximum ff toggle rate 2 1/(t ch + t cl ) 167 125 125 mhz f max2 maximum internal frequency 2 1/(t supal + t cf )877465mhz f max3 maximum external frequency 2 1/(t supal + t co )776659mhz t buf output buffer delay time 1.5 1.5 1.5 ns t pdf_pal input (or feedback node) to internal feedback node delay time through pal 2 0.5 2 10.5 2 13.5 ns t pdf_pla input (or feedback node) to internal feedback node delay time through pal+pla 311313316ns t cf clock to internal feedback node delay time 5.5 6.5 7.5 ns t init delay from valid v dd to valid reset 50 50 50 s t er input to output disable 3 12.5 14 17 ns t ea input to output valid 12.5 14 17 ns t rp input to register preset 14 16 19 ns t rr input to register reset 14 16 19 ns notes: 1. specifications measured with one output switching. see figure 6 and ta b l e 6 for derating. 2. this parameter guaranteed by design and characterization, not by test. 3. output c l = 5 pf.
r xcr3128: 128 macrocell cpld ds034 (v1.2) august 10, 2000 www.xilinx.com 12 1-800-255-7778 dc electrical characteristics for industrial grade devices industrial: -40 c t amb +85 c; 3.0v v cc 3.6v symbol parameter test conditions min. max. unit v il input voltage low v cc = 3.0v 0.8 v v ih input voltage high v cc = 3.6v 2.0 v v i input clamp voltage v cc = 3.0v, i in = -18 ma -1.2 v v ol output voltage low v cc = 3.0v, i ol = 8 ma 0.5 v v oh output voltage high v cc = 3.0v, i oh = -8 ma 2.4 v i i input leakage current v in = 0 to v cc -10 10 a i oz 3-stated output leakage current v in = 0 to v cc -10 10 a i ccq 1 standby current v cc = 3.6v, t amb = -40 c75 a i ccd 1, 2 dynamic current v cc = 3.6v, t amb = -40 c at 1 mhz 2 ma v cc = 3.6v, t amb = -40 c at 50 mhz 50 ma i os short circuit output current 3 one pin at a time for no longer than 1 second -50 -130 ma c in input pin capacitance 3 t amb = 25 c, f = 1 mhz 8 pf c clk clock input capacitance 3 t amb = 25 c, f = 1mhz 5 12 pf c i/o i/o pin capacitance 3 t amb = 25 c, f = 1mhz 10 pf notes: 1. see table 1 on page 6 for typical values. 2. this parameter measured with a 16-bit, loadable up/down counter loaded into every logic block, with all outputs disabled and unloaded. inputs are tied to v cc or ground. this parameter guaranteed by design and characterization, not testing. 3. typical values, not tested.
r xcr3128: 128 macrocell cpld 13 www.xilinx.com ds034 (v1.2) august 10, 2000 1-800-255-7778 ac electrical characteristics 1 for industrial grade devices industrial: -40 c t amb +85 c; 3.0v v cc 3.6v symbol parameter 12 15 unit min. max. min. max. t pd_pal propagation delay time, input (or feedback node) to output through pal 2 12 2 15 ns t pd_pla propagation delay time, input (or feedback node) to output through pal + pla 3 14.5 3 17.5 ns t co clock to out (global synchronous clock from pin) 2 7.5 2 9 ns t su_pal setup time (from input or feedback node) through pal 7 8 ns t su_pla setup time (from input or feedback node) through pal + pla 9.5 10.5 ns t h hold time 00ns t ch clock high time 3 4 ns t cl clock low time 3 4 ns t r input rise time 20 20 ns t f input fall time 20 20 ns f max1 maximum ff toggle rate 2 1/(t ch + t cl ) 167 125 mhz f max2 maximum internal frequency 2 1/(t supal + t cf )7765mhz f max3 maximum external frequency 2 1/(t supal + t co )6959mhz t buf output buffer delay time 1.5 1.5 ns t pdf_pal input (or feedback node) to internal feedback node delay time through pal 2 10.5 2 13.5 ns t pdf_pla input (or feedback node) to internal feedback node delay time through pal+pla 313316ns t cf clock to internal feedback node delay time 6 7.5 ns t init delay from valid v cc to valid reset 50 50 s t er input to output disable 3 13 15.5 ns t ea input to output valid 13 15.5 ns t rp input to register preset 15 17 ns t rr input to register reset 15 17 ns notes: 1. specifications measured with one output switching. see figure 6 and table 8 for derating. 2. this parameter guaranteed by design and characterization, not by test. 3. output c l = 5 pf.
r xcr3128: 128 macrocell cpld ds034 (v1.2) august 10, 2000 www.xilinx.com 14 1-800-255-7778 switching characteristics the test load circuit and load values for the ac electrical characteristics are illustrated below. v cc v in v out c1 r1 r2 s1 s2 component values r1 390 ? r2 390 ? c1 35 pf measurement s1 s2 t pzh open closed t pzl closed closed t p closed closed sp00477 note: for t phz and t plz c = 5 pf, and 3-state levels are measured 0.5v from steady-state active level. figure 6: t pd_pal vs. output switching number of outputs switching 1 2 4 8 12 16 7.5 t pd_pal (ns) 7.9 8.3 8.7 v dd = 3.3v, 25 c sp00466a 9.1 figure 7: voltage waveform table 6: t pd_pal vs. number of outputs switching (v cc = 3.3 v, t = 25 c) number of outputs 12481216 typical (ns) 7.9 8 8.1 8.3 8.4 8.6 90% 10% 1.5ns 1.5ns +3.0v 0v t r t f measurements: all circuit delays are measured at the +1.5v level of inputs and outputs, unless otherwise specified. input pulses sp00368
r xcr3128: 128 macrocell cpld 15 www.xilinx.com ds034 (v1.2) august 10, 2000 1-800-255-7778 pin function and layout xcr3128: 100-pin and 160-pin pqfp pin function table pin # function pqfp pin # function pqfp pin # function pqfp pin # function pqfp 100-pin 160-pin 100-pin 160-pin 100-pin 160-pin 100-pin 160-pin 1i/o-a5 nc 41 v cc i/o-c0 81 i/o-h7 nc 121 - i/o-h0 2 i/o-a4 nc 42 i/o-e0/clk1 gnd 82 i/o-h8 nc 122 - i/o-h2 3 i/o-a2 nc 43 i/o-e2 i/o-d15 83 i/o-h10 nc 123 - i/o-h3 4 i/o-a0 nc 44 i/o-e4 nc 84 v cc nc 124 - nc 5v cc nc 45 gnd nc 85 i/o-h12 nc 125 - nc 6 i/o-b15 (tdi) nc 46 i/o-e5 nc 86 i/o-h13 nc 126 - nc 7 i/o-b13 nc 47 i/o-e7 nc 87 i/o-h15 nc 127 - nc 8i/o-b12 v cc 48 i/o-e8 i/o-d13 88 gnd i/o-f2 128 - i/o-h4 9 i/o-b10 i/o-b15 (tdi) 49 i/o-e10 i/o-d12 89 in0/ck0 i/o-f3 129 - i/o-h5 10 i/o-b8 i/o-b13 50 i/o-e12 i/o-d11 90 in2/gtsn i/o-f4 130 - i/o-h7 11 i/o-b7 i/o-b12 51 i/o-e13 i/o-d10 91 in1 i/o-f5 131 - i/o-h8 12 i/o-b5 i/o-b11 52 i/o-e15 i/o-d8 92 in3 i/o-f7 132 - i/o-h10 13 gnd i/o-b10 53 v cc i/o-d7 93 v cc i/o-f8 133 - v cc 14 i/o-b4 i/o-b8 54 i/o-f0 i/o-d5 94 i/o-a15/ck3 i/o-f10 134 - i/o-h11 15 i/o-b2 i/o-b7 55 i/o-f2 v cc 95 i/o-a13 gnd 135 - i/o-h12 16 i/o-b0 i/o-b5 56 i/o-f4 i/o-d4 96 i/o-a12 i/o-f11 136 - i/o-h13 17 i/o-c15 (tms) gnd 57 i/o-f5 i/o-d3 97 gnd i/o-f12 137 - i/o-h15 18 i/o-c13 i/o-b4 58 i/o-f7 i/o-d2 98 i/o-a10 i/o-f13 138 - gnd 19 i/o-c12 i/o-b3 59 i/o-f8 i/0-d0/clk2 99 i/o-a8 i/o-f15 (tck) 139 - in0/ck0 20 v cc i/o-b2 60 i/o-f10 gnd 100 i/o-a7 i/o-g0 140 - in2/gtsn 21 i/o-c10 i/o-b0 61 gnd v cc 101 - i/o-g2 141 - in1 22 i/o-c8 i/o-c15 (tms) 62 i/o-f12 i/0-e0/clk1 102 - i/o-g3 142 - in3 23 i/o-c7 i/o-c13 63 i/o-f13 i/o-e2 103 - i/o-g4 143 - v cc 24 i/o-c5 i/o-c12 64 i/o-f15 (tck) i/o-e3 104 - v cc 144 - i/o-a0/ck3 25 i/o-c4 i/o-c11 65 i/o-g0 i/o-e4 105 - i/o-g5 145 - i/o-a13 26 i/o-c2 v cc 66 i/o-g2 gnd 106 - i/o-g7 146 - i/o-a12 27 i/o-c0 i/o-c10 67 i/o-g4 i/0-e5 107 - i/o-g8 147 - i/o-a11 28 gnd i/o-c8 68 v cc i/0-e7 108 - i/o-g10 148 - gnd 29 i/o-d15 i/o-c7 69 i/o-g5 i/0-e8 109 - i/o-g11 149 - i/o-a10 30 i/o-d13 i/o-c5 70 i/o-g7 i/0-e10 110 - i/o-g12 150 - i/o-a8 31 i/o-d12 i/o-c4 71 i/o-g8 i/o-e11 111 - i/o-g13 151 - i/o-a7 32 i/o-d10 i/o-c3 72 i/o-g10 i/0-e12 112 - i/o-g15 (tdo) 152 - i/o-a5 33 i/o-d8 i/o-c2 73 i/o-g12 i/0-e13 113 - gnd 153 - i/o-a4 34 i/o-d7 nc 74 i/o-g13 nc 114 - nc 154 - nc 35 i/o-d5 nc 75 i/o-g15 (tdo) nc 115 - nc 155 - nc 36 v cc nc 76 gnd nc 116 - nc 156 - nc 37 i/o-d4 nc 77 i/o-h0 nc 117 - nc 157 - nc 38 i/o-d2 nc 78 i/o-h2 i/o-e15 118 - nc 158 - i/o-a3 39 i/o-d0/ck2 nc 79 i/o-h4 v cc 119 - nc 159 - i/o-a2 40 gnd nc 80 i/o-h5 i/o-f0 120 - nc 160 - i/o-a0
r xcr3128: 128 macrocell cpld ds034 (v1.2) august 10, 2000 www.xilinx.com 16 1-800-255-7778 xcr3128: 84-pin plcc, 100-pin vqfp, and 128-pin tqfp pin function table pin # function pin # function pin # function pin # function plcc vqfp tqfp plcc vqfp tqfp plcc vqfp tqfp plcc vqfp tqfp 1 in1 i/o-a2 i/o-a3 33 i/o-d15 i/o-d5 nc 65 i/o-g4 i/o-g4 i/o-e15 97 - i/o-a8 nc 2 in3 i/o-a0 i/o-a2 34 i/o-d12 v cc nc 66 v cc v cc v cc 98 - i/o-a7 nc 3v cc v cc i/o-a0 35 i/o-d10 i/o-d4 nc 67 i/o-g7 i/o-g5 i/o-f0 99 - i/o-a5 nc 4 i/o-a15/ clk3 i/o-b15 (tdi) nc 36 i/o-d8 i/o-d2 i/o-c0 68 i/o-g8 i/o-g7 nc 100 - i/o-a4 i/o-h0 5 i/o-a13 i/o-b13 nc 37 i/o-d7 i/o-d0/ clk2 gnd 69 i/o-g10 i/o-g8 nc 101 - - i/o-h2 6 i/o-a12 i/o-b12 nc 38 v cc gnd i/o-d15 70 i/o-g12 i/o-g10 nc 102 - - i/o-h3 7 gnd i/o-b10 v cc 39 i/o-d4 v cc i/o-d13 71 i/o-g15 (tdo) i/o-g12 i/o-f2 103 - - i/o-h4 8 i/o-a10 i/o-b8 i/o-b15 (tdi) 40 i/o-d2 i/o-e0/ clk1 i/o-d12 72 gnd i/o-g13 i/o-f3 104 - - i/o-h5 9 i/o-a7 i/o-b7 i/o-b13 41 i/o-d0/c lk2 i/o-e2 i/o-d11 73 i/o-h2 i/o-g15 (tdo) i/o-f4 105 - - i/o-h7 10 i/o-a5 i/o-b5 i/o-b12 42 gnd i/o-e4 i/o-d10 74 i/o-h4 gnd i/o-f5 106 - - i/o-h8 11 i/o-a4 gnd i/o-b11 43 v cc gnd i/o-d8 75 i/o-h5 i/o-h0 i/o-f7 107 - - i/o-h10 12 i/o-a2 i/o-b4 i/o-b10 44 i/o-e0/c lk1 i/o-e5 i/o-d7 76 i/o-h7 i/o-h2 i/o-f8 108 - - v cc 13 v cc i/o-b2 i/o-b8 45 i/o-e2 i/o-e7 i/o-d5 77 i/o-h10 i/o-h4 i/o-f10 109 - - i/o-h11 14 i/o-b15 (tdi) i/o-b0 i/o-b7 46 i/o-e4 i/o-e8 v cc 78 v cc i/o-h5 gnd 110 - - i/o-h12 15 i/o-b12 i/o-c15 (tms) i/o-b5 47 gnd i/o-e10 i/o-d4 79 i/o-h12 i/o-h7 i/o-f11 111 - - i/o-h13 16 i/o-b10 i/o-c13 gnd 48 i/o-e7 i/o-e12 i/o-d3 80 i/o-h13 i/o-h8 i/o-f12 112 - - i/o-h15 17 i/o-b8 i/o-c12 i/o-b4 49 i/o-e8 i/o-e13 i/o-d2 81 i/o-h15 i/o-h10 i/o-f13 113 - - gnd 18 i/o-b7 v cc i/o-b3 50 i/o-e10 i/o-e15 i/o-d0/c lk2 82 gnd v cc i/o-f15 (tck) 114 - - in0/clk0 19 gnd i/o-c10 i/o-b2 51 i/o-e12 v cc gnd 83 in0/ clk0 i/o-h12 i/o-g0 115 - - in2/gtsn 20 i/o-b4 i/o-c8 i/o-b0 52 i/o-e15 i/o-f0 v cc 84 in2/gtsn i/o-h13 i/o-g2 116 - - in1 21 i/o-b2 i/o-c7 i/o-c15 (tms) 53 v cc i/o-f2 i/o-e0/ clk1 85 - i/o-h15 i/o-g3 117 - - in3 22 i/o-b0 i/o-c5 i/o-c13 54 i/o-f2 i/o-f4 i/o-e2 86 - gnd i/o-g4 118 - - v cc 23 i/o-c15 (tms) i/o-c4 i/o-c12 55 i/o-f4 i/o-f5 i/o-e3 87 - in0/clk0 v cc 119 - - i/o-a15/ clk3 24 i/o-c13 i/o-c2 i/o-c11 56 i/o-f5 i/o-f7 i/o-e4 88 - in2/gtsn i/o-g5 120 - - i/o-a13 25 i/o-c12 i/o-c0 v cc 57 i/o-f7 i/o-f8 gnd 89 - in1 i/o-g7 121 - - i/o-a12 26 v cc gnd i/o-c10 58 i/o-f10 i/o-f10 i/o-e5 90 - in3 i/o-g8 122 - - i/o-a11 27 i/o-c10 i/o-d15 i/o-c8 59 gnd gnd i/o-e7 91 - v cc i/o-g10 123 - - gnd 28 i/o-c7 i/o-d13 i/o-c7 60 i/o-f12 i/o-f12 i/o-e8 92 - i/o-a15/c lk3 i/o-g11 124 - - i/o-a10 29 i/o-c5 i/o-d12 i/o-c5 61 i/o-f13 i/o-f13 i/o-e10 93 - i/o-a13 i/o-g12 125 - - i/o-a8 30 i/o-c4 i/o-d10 i/o-c4 62 i/o-f15 (tck) i/o-f15 (tck) i/o-e11 94 - i/o-a12 i/o-g13 126 - - i/o-a7 31 i/o-c2 i/o-d8 i/o-c3 63 i/o-g0 i/o-g0 i/o-e12 95 - gnd i/o-g15 (tdo) 127 - - i/o-a5 32 gnd i/o-d7 i/o-c2 64 i/o-g2 i/o-g2 i/o-e13 96 - i/o-a10 gnd 128 - - i/o-a4
r xcr3128: 128 macrocell cpld 17 www.xilinx.com ds034 (v1.2) august 10, 2000 1-800-255-7778 84-pin plcc 100-pin pqfp 100-pin vqfp 128-pin tqfp 160-pin pqfp plcc 11 1 75 12 32 74 54 33 53 sp00467a sp00468a qfp 100 81 1 30 80 51 31 50 pqfp sp00485a tqfp 100 76 1 25 75 51 26 50 vqfp sp00469b lqfp 128 1 38 39 65 64 103 102 tqfp sp00470b pqfp 160 1 40 41 81 80 121 120
r xcr3128: 128 macrocell cpld ds034 (v1.2) august 10, 2000 www.xilinx.com 18 1-800-255-7778 ordering information revision table component availability pins 84 100 128 160 type plastic plcc plastic pqfp plastic vqfp plastic tqfp plastic pqfp code pc84 pq100 vq100 tq128 pq160 xcr3128 -15 c, i c, i c, i c, i c, i -12 c, i c, i c, i c, i c, i -10 c c c c c date version # revision 8/4/99 1.0 initial xilinx release 2/10/00 1.1 converted to xilinx format and updated. 8/10/00 1.2 updated pinout tables. example: xcr3128 -10 pc 84 c temperature range number of pins package type speed options -15: 15 ns pin-to-pin delay -12: 12 ns pin-to-pin delay -10: 10 ns pin-to-pin delay temperature range c = commercial, t a = 0 c to +70 c i = industrial, t a = ? 40 c to +85 c packaging options pc84: 84-pin plcc pq100: 100-pin pqfp vq100: 100-pin vqfp tq128: 128-pin tqfp pq160: 160-pin pqfp device type speed options

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